Mobile devices or devices, such as but not limited to personal data appliances, cellular phones, radios, pagers, lap top computers, and the like are required to operate for relatively long periods before being recharged. These mobile devices usually include one or more processors as well as multiple memory modules and other peripheral devices.
The power consumption of a transistor-based device is highly influenced by leakage currents that flow through the transistor. The leakage current is responsive to various parameters including the threshold voltage (Vt) of the transistor, the temperature of the transistor, supply voltage and the like. Transistors that have higher Vt are relatively slower but have lower leakage currents while transistors that have lower Vt are relatively faster but have higher leakage current.
In order to reduce the power consumption of mobile devices various power consumption control techniques were suggested. A first technique uses domino circuits that include both high threshold voltage transistors and low threshold voltage transistors. U.S. patent application number 2004/0008056 of Kursun et al., which is incorporated herein by reference, discloses a domino circuit that is configured such as to reduce power consumption, for example by limiting the energy consumed during power switching.
Yet another technique is based upon creating a stack effect that involves shutting down multiple transistors of the same type that are serially connected to each other. U.S. Pat. No. 6,169,419 of De et al., which is incorporated herein by reference, discloses a method and apparatus for reducing standby leakage current using a transistor stack effect. De describes a logic that has both a pull up path and a pull down path.
A further technique includes reducing the clock frequency of the mobile device. Yet a further technique is known as dynamic voltage scaling (DVS) or alternatively is known as dynamic voltage and frequency scaling (DVFS) and includes altering the voltage that is supplied to a processor as well as altering the frequency of a clock signal that is provided to the processor in response to the computational load demands (also referred to as throughput) of the processor. Higher voltage levels are associated with higher operating frequencies and higher computational load but are also associated with higher energy consumption.
Very aggressive DVS techniques are illustrated in “DVS for On-Chip Bus Designs Based On Timing Error Correction”, H. Kaul, D. Sylvester, D. Blaauw, T. Mudge and T. Austin, Proceedings of the Design, Automation and Test in Europe Conference and Exhibition (DATE'05) and “Razor: A Low Power Pipeline Based on Circuit-Level Timing Speculation”, D. Ernst, N. S. Kim, S. Das, S. Pant, R. Rao, T. Pham, C. Ziesler, D. Blaauw, T. Austin, K. Flautner and T. Mudge, 36TH Annual International Symposium on Microarchitecture (MICRO-36), December 2003. These aggressive DVS technique are based upon the assumption that power savings can be increased if the supplied voltage level (and clock signal frequency) will be responsive to error occurring in a circuit and not be responsive to the voltage level (and clock signal frequency) that should be supplied to a theoretical circuit that is characterized by worst-case scenarios of environment and process variations. In a nutshell the supplied voltage level (and clock frequency) are lowered until error are being detected. It is noted that the error rate dramatically increases when the voltage level decreases below a certain voltage level.
FIG. 1 illustrates a prior art flip-flop 10 as illustrated in the first article while FIG. 2 illustrates a prior art flip-flop 11 as illustrated in the second article. Prior art flip-flop 11 differs from prior art flip-flop 10 by including a meta-stable detector 50 and an additional logical gate 60 that is connected to the output of the meta-stable detector 50 and to comparator 28 that compares the output of first latch 41 and shadow latch 43.
Flip-flop 10 includes input inverter 12, output inverter 24, first latch 41, second latch 42, shadow latch 43 and comparator 28. The first and second latches 41 and 42 are serially connected to each other. The outputs of second transfer gate 18 and shadow latch 43 are connected to inputs of comparator 28. The output of comparator 28 generates an error indication Error. First latch 41 includes first transfer gate 14 that is serially connected to first inverter 16. The output of first inverter 16 is connected to a first input of first multiplexer 26. Another input of first multiplexer 26 is connected to an output of shadow latch 43. First multiplexer 26 is controlled by Error and its output is connected to the input of first inverter 16. Second latch 42 includes second transfer gate 18 followed by a pair of inversely connected second and third inverters 20 and 22. The output of second latch 42 is connected to an input of output latch 24. The output of second transfer gate 18 is connected to an input of comparator 28.
The input of first transfer gate 14 and of shadow transfer gate 30 are connected to an output of input inverter 12. First transfer gate 14 is clocked by a clock signal (Clk) and shadow transfer gate 30 is clocked by a delayed clock signal (Clk_delayed). Second transfer gate 18 of second latch 42 is clocked by an inverted clock signal (Clk_inv). Accordingly, first latch 41 latches data at the rising edge of Clk, second latch 42 latches data at the falling edge of Clk and shadow latch 43 latches data at a certain delay (usually slightly before the falling edge of Clk) from the rising edge of Clk.
Prior art flip-flop 11 further includes a meta-stable detector 50 that is connected to the output of second latch 42 and its output is connected to a first input of or gate 60. The other input of OR gate 60 is connected to the output of comparator 28. The output of OR gate 60 provided error signal Error.
Meta-stable detector 50 includes fourth till sixth inverters 52, 54 and 56 and an AND logic gate 58. The output of second latch 42 is connected to the inputs of fourth and sixth inverters 52 and 56. The output of sixth inverter 56 is connected to an input of AND logic gate 58. The fifth inverter 54 is connected between the AND logic gate 58 and the fourth inverter 52.
Both flip-flops 10 and 11 perform error detection by comparing between data stored at shadow latch 43 and data stored at first latch 41, wherein the comparison occurs at the falling edge (after 50% of the clock cycle) of the clock cycle. Accordingly, only a small portion of the clock cycle is allocated for error detection propagation.
In addition, error recovery takes another clock cycle and data stored at shadow latch 43 is sent to first latch 41 via first multiplexer 26.
FIG. 3 is a timing diagram of a clock signal and an effective clock signal that illustrates loss of one clock cycle due to each error recovery session. Curve 290 (referred to as Clk 290) eight clock cycles (CYCLE1-CYCLE8) of clock signal Clk 290. Curve 300 (referred to as effective clock signal) illustrates the clock cycles that are used for data processing. At CYCLE3 and CYCLE 7 a clock recovery process occurred, thus these cycle were not used for data processing and accordingly were omitted from curve 300.
There is a growing need to find effective devices and methods for power management.